As the level of semiconductor process integration has progressed, advances in the technology have been largely focused on reducing feature sizes and layout geometry of active devices as well as increasing the density of metallization. However, in many instances, reductions in the area requirements for passive devices have not kept pace with reduced feature sizes of active devices and metallization. For example, the layout area required for resistors is largely determined by the sheet resistance. The physical size of a capacitor network is limited by several factors, including the required area of the capacitor plates as well as the thickness of the intervening dielectric. That is, as dielectric thickness decreases the capacitance increases such that the capacitor becomes less area consuming. Generally, reduction in layout area for resistor and capacitor structures has been largely considered a function of material selection. There is a need to provide additional methods and designs so that further reductions in area requirements of passive structures will not depend solely on development of new materials. In particular, further reduction in area requirements for capacitors will enable further improvement in the level of integration for both digital and analog circuitry. Prior efforts to increase capacitance without increasing area consumed over a semiconductor region were effected by forming multiple capacitors on separate metal levels and connecting these in parallel.
In the past, in order to provide increased capacitance to meet circuit requirements, capacitors formed on separate metal levels have been wired in parallel circuitry. Another means of achieving high capacitance has been reduction in the thickness of the dielectric layer between the capacitor plates.